The present invention generally relates to semiconductor devices for use in semiconductor integrated circuits, and more particularly relates to semiconductor devices that are formed in integrated circuits and constitute constant voltage devices used to raise internal voltage, for example. The present invention also relates to methods for fabricating the semiconductor devices.
In a booster provided inside an integrated circuit, a constant voltage device, which is called a xe2x80x9cclamping diodexe2x80x9d, has been conventionally used to fix an increased voltage at a given voltage. Such a constant voltage device, also known as a Zener diode, uses the reverse breakdown phenomenon that occurs at a pn junction formed by a semiconductor substrate and a doped layer formed in the semiconductor substrate in order to obtain a given constant voltage.
(First Conventional Case)
Hereinafter, a constant voltage device in accordance with a first conventional case will be described with reference to FIG. 7. As shown in FIG. 7, the constant voltage device of the first conventional case includes an n-type doped layer 103 and a p-type doped layer 104. The n-type doped layer 103 is formed by doping with n-type impurity ions a part of the upper portion of a p-type semiconductor substrate 101, in an active region 100 surrounded by an isolating oxide film 102. The p-type doped layer 104 is formed by doping the remaining part thereof with p-type impurity ions. In this case, a pn junction is formed in the substantially central portion of the active region 100 by the n-type and p-type doped layers 103 and 104.
An interlevel dielectric film 105 is formed on the semiconductor substrate 101. In the interlevel dielectric film 105, plugs 106 of tungsten are formed to be electrically connected to the n-type and p-type doped layers 103 and 104, respectively. Further, interconnects 107 made of aluminum are formed on the interlevel dielectric film 105 in such a manner that the interconnects 107 establish connection with the respective plugs 106.
In the constant voltage device of the first conventional case, the constant voltage of the device is determined by the reverse breakdown voltage at the pn junction formed by the n-type and p-type doped layers 103 and 104. Specifically, when a reverse voltage exceeding the constant voltage is applied to the region between the n-type and p-type doped layers 103 and 104, the reverse current resulting from the Zener effect or the avalanche effect flows between the n-type and p-type doped layers 103 and 104. This phenomenon allows the voltage between the n-type and p-type doped layers 103 and 104 to be substantially maintained at a constant voltage, even if a large voltage is applied.
(Second Conventional Case)
Next, a constant voltage device in accordance with a second conventional case will be described with reference to FIG. 8. The constant voltage device shown in FIG. 8 has a structure in which a pn junction is formed between a p-type semiconductor substrate 101 and an n-type doped layer 103 formed in an upper portion of an active region 100 in the p-type semiconductor substrate 101.
In the constant voltage device of the second conventional case, the constant voltage of the device is determined by the reverse breakdown voltage at the pn junction formed by the n-type doped layer 103 and the semiconductor substrate 101. Specifically, when a reverse voltage exceeding the constant voltage is applied between an aluminum interconnect 107 and the p-type semiconductor substrate 101, the resulting reverse current due to the Zener effect or the avalanche effect flows between the semiconductor substrate 101 and the n-type doped layer 103. Even if a large voltage is applied, the voltage between the aluminum interconnect 107 and the semiconductor substrate 101 is thus substantially maintained at a constant value.
The constant voltage devices of the first and second conventional cases both have the following problems, however.
First, in the constant voltage device of the first conventional case, the doped layers 103 and 104 of the mutually differing conductivity types are both formed side by side in the semiconductor-substrate 101 active region 100 in a planar direction of the substrate principal surface, leading to the problem that the constant voltage device accounts for a large area in an integrated circuit. Further, since the constant voltage of the device is determined by the reverse breakdown voltage applied to the pn junction that is the interface formed between the n-type and p-type doped layers 103 and 104, impurity concentration in at least one of the n-type and p-type doped layers 103 and 104 has to be adjusted in order to obtain a desired constant voltage.
In the constant voltage device of the second conventional case, on the other hand, the doped layer is of n-type alone, allowing the area occupied by the device in an integrated circuit to be reduced. As mentioned above, however, the constant voltage of the device is determined by the reverse breakdown voltage applied to the pn junction, that is, the interface formed between the n-type doped layer 103 and the p-type semiconductor substrate 101. Thus, as in the first conventional case, impurity concentration in at least one of the semiconductor substrate 101 and the n-type doped layer 103 has to be adjusted in order to obtain a desired constant voltage.
Nevertheless, generally, in integrated circuits, an n-type doped layer 103, a p-type doped layer 104, or a semiconductor substrate 101 is often used as a well shared by other semiconductor devices. Thus, the level of freedom at which impurity concentration in the n-type doped layer 103, p-type doped layer 104, or semiconductor substrate 101 may be independently adjusted is low. Consequently, it is very difficult to establish an intended constant voltage for the constant voltage device.
Moreover, the constant voltage devices of the first and second conventional cases also have the problem that the reverse breakdown voltage changes with time.
FIG. 9A shows the relationship between duration of applied constant current stress and variation in reverse breakdown voltage in the constant voltage devices of the first and second conventional cases. FIG. 9B shows the relationship between time for which the constant voltage devices are left to stand under high temperature conditions after constant current stress has been applied, and variation in reverse breakdown voltage. It should be understood that the conditions under which the measurements shown in FIG. 9A were carried out include an applied current of 200 xcexcA and an evaluation temperature of 125xc2x0 C. The measurements shown in FIG. 9B were made under conditions in which a current of 2 mA was applied for 3.5 hours, and thereafter the constant voltage devices were left to stand under a temperature of 150xc2x0 C. The line plotted with circles represents the first conventional case, while the line plotted with triangles represents the second conventional case. As can be seen from FIGS. 9A and 9B, the variation in the constant voltage is as much as 1 to 1.2 V in the first conventional case, and the variation in the constant voltage is about 0.7 to 0.9 V in the second conventional case.
The present invention was made in view of the conventional problems, and it is therefore an object thereof to facilitate obtaining a desired constant voltage in a semiconductor device, while reducing the area occupied by the device, and at the same time to prevent reverse breakdown voltage therein from varying with time.
In order to achieve the object, a semiconductor device according to the present invention has a structure in which in at least one of p-type and n-type doped layers that form a pn junction, a portion adjacent to (in the vicinity of) an isolation film has a lower impurity concentration than the other portion.
Such a structure allows the position at which reverse breakdown occurs in the pn junction to be kept apart from the region adjacent to the isolation film, which, according to the following findings, prevents variation in reverse breakdown voltage with time.
The present inventor, after making various studies as to why it is difficult to obtain a desired constant voltage, that is, a desired design voltage for a clamping diode and other semiconductor devices and as to the cause of the large variation with time indicated in FIGS. 9A and 9B, reached the following conclusions and findings.
First, the case with the constant voltage device of the first conventional case will be described.
In the constant voltage device of the first conventional case shown in FIG. 7, a reverse breakdown phenomenon caused by a reverse voltage applied to the n-type and p-type doped layers 103 and 104 creates electron-hole pairs at the pn junction (identified by the reference mark A) formed by n-type and p-type doped layers 103 and 104. Holes, for the most part, of the electron-hole pairs are injected into the interlevel dielectric film 105 on the p-type doped layer 104 through a portion of the p-type doped layer 104 located in the vicinity of the pn junction. On the other hand, electrons of the electron-hole pairs are injected into the interlevel dielectric film 105 on the n-type doped layer 103 through a portion of the n-type doped layer 103 located in the vicinity of the pn junction. This results in increase in the reverse breakdown voltage such that the reverse breakdown voltage varies due to application of constant current stress as shown in FIG. 9A.
As shown in FIG. 9A, however, there are cases in which despite the fact that a junction breakdown phenomenon has occurred at the top end of the pn junction, the reverse breakdown voltage apparently does not vary. This is because electrons and holes are both injected into the interlevel dielectric film 105 at an early stage and neutralize the electric field. The reverse breakdown voltage therefore does not vary.
Even in such a case, however, when the constant voltage device is left to stand under high temperature conditions (150xc2x0 C.) after constant current stress has been applied, the electrons, easy to be released by heat, are rapidly released from the interlevel dielectric film 105 into other portions before the holes are released, thereby causing the reverse breakdown voltage to increase as shown in FIG. 9B.
Next, the case with the constant voltage device of the second conventional case shown in FIG. 8 will be described.
FIGS. 1A through 1C are enlarged views showing boundary portions between the isolating oxide film 102 and the pn junction formed by the p-type semiconductor substrate 101 and the n-type doped layer 103.
As shown in FIG. 1A, when a voltage exceeding the reverse breakdown voltage is applied, electron-hole pairs are created due to the reverse breakdown phenomenon at the pn junction formed by the n-type doped layer 103 and the p-type semiconductor substrate 101. Since the semiconductor substrate 101 has an impurity concentration lower than the n-type doped layer 103, the depletion layer expands more on the semiconductor substrate 101 side than on the n-type doped layer 103 side. Further, the breakdown voltage in the pn junction plane is lowest in a portion thereof in contact with the isolating oxide film 102, in which portion the junction breakdown therefore happens. As a result, holes, for the most part, of the electron-hole pairs generated by the breakdown phenomenon are injected from a portion of the semiconductor substrate 101 located in the vicinity of the pn junction edge into the isolating oxide film 102 adjacent to the pn junction edge. On the other hand, electrons of the electron-hole pairs are injected from a portion of the n-type doped layer 103 located in the vicinity of the pn junction edge into the isolating oxide film 102 adjacent to the pn junction edge. Consequently, as shown in FIG. 1B, the injected electrons and holes act to expand the depletion layer. Where the depletion layer is in the p-type semiconductor substrate 101 having the lower impurity concentration than the n-type doped layer 103, in particular, expands more, whereby the electric field in the depletion layer in the vicinity of the isolating oxide film 102 is weakened. This results in increasing the reverse breakdown voltage, between the n-type doped layer 103 (or the aluminum interconnect 107) and the semiconductor substrate 101, required to increase the voltage between the p-type semiconductor substrate 101 and the n-type doped layer 103 up to the reverse breakdown voltage at the pn junction.
For the above reasons, the variation in the reverse breakdown voltage due to application of constant current stress shown in FIG. 9A is caused.
Moreover, as shown in FIG. 1C, when the constant voltage device is left to stand under high temperature conditions after constant current stress has been applied, the depletion layer further expands in a portion in the pn junction in the vicinity of the isolating oxide film 102 because the electrons are easy to be released from the isolating oxide film 102 by heat. As mentioned above, these are the reasons why the reverse breakdown voltage varies when the constant voltage device is left to stand under high temperature conditions after constant current stress has been applied, as shown in FIG. 9B. Semicircles and semi-ellipses shown in the isolating oxide film 102 in FIGS. 1A through 1C are graphs respectively schematically representing relationships between electron/hole density and location.
As mentioned above, in a semiconductor integrated circuit incorporating either type of conventional constant voltage device, the reverse breakdown voltage varies as compared to its given constant voltage. The constant voltage device thus cannot fulfill its functions as a constant voltage device.
In view of these facts, the present inventor reached the findings that when a constant voltage device has a structure in which doped layers forming a pn junction are provided as first and second doped layers forming a two-layer-stacked structure perpendicular with respect to the substrate surface of a semiconductor substrate, a desired constant voltage can be easily obtained while the area occupied by the constant voltage device in an integrated circuit is reduced. Further, the present inventor discovered that in the constant voltage device of the second conventional case, the reverse breakdown phenomenon that occurs at the pn junction occurs in the vicinity of the isolating oxide film. Based on this, he found out that if impurity concentration is adjusted in at least one of the first and second doped layers so that a portion thereof located in the vicinity of the isolation film has a lower impurity concentration than the rest, variation in the reverse breakdown voltage with time can be controlled.
Specifically, an inventive semiconductor device includes: a semiconductor region defined by an isolation film; a first doped layer formed in the semiconductor region and having a conductivity type different than the semiconductor region; and a second doped layer formed in the semiconductor region in such a manner that the second doped layer is in contact with an upper or lower side of the first doped layer and that an end portion of the second doped layer is in contact with the isolation film. The second doped layer has the same conductivity type as the semiconductor region. A portion of the second doped layer adjacent the isolation film has an impurity concentration lower that the remaining portion of the second doped layer.
In the inventive semiconductor device, the position at which reverse breakdown occurs in the pn junction can be kept apart from the isolation film. Electrons and holes generated by junction breakdown are thus prevented from being injected into the isolation film, thereby preventing variation in the reverse breakdown voltage with time.
In the inventive semiconductor device, the second doped layer is preferably formed to cover the lower side of the first doped layer.
In the inventive semiconductor device, the first doped layer is preferably formed in such a manner that the lateral of the first doped layer is spaced apart from the side face of the isolation film.
Then, the first doped layer is kept apart from the isolation film, as a result of which, the position in the pn junction at which reverse junction breakdown occurs can be completely separate from a portion adjacent the isolation film, thereby significantly suppressing electrons and holes generated by junction breakdown from being injected into the isolation film.
In that case, it is preferable that the second doped layer also covers the lateral of the first doped layer.
Further, in that case, the first doped layer is preferably formed in an upper portion of the semiconductor region, the second doped layer preferably reaches the surface of the semiconductor region, and in the second doped layer, a portion in the vicinity of that surface preferably has a lower impurity concentration than the other portion, except the portion adjacent the isolation film.
In the inventive semiconductor device, the semiconductor region is preferably a substrate made of semiconductor, the first doped layer is preferably formed in an upper portion of the substrate, and a plug that is electrically connected to the first doped layer is preferably formed on the first doped layer.
In the inventive semiconductor device, the second doped layer is preferably formed by rotational implant (angled implant) of an impurity from at least three directions.
An inventive method for fabricating a semiconductor device includes the steps of: (a) selectively forming an isolation film in a semiconductor region, (b) forming a first doped layer having a conductivity type different than the semiconductor region, in an area located in the semiconductor region and surrounded by the isolation film, and (c) forming a second doped layer having the same conductivity type as the semiconductor region, in the semiconductor region in such a manner that the second doped layer is in contact with the isolation film and the first doped layer. In the step (c), impurity ions are implanted at angles with respect to the normal to the surface of the semiconductor region, from at least three mutually differing directions, thereby forming the second doped layer in which a portion adjacent the isolation film has a lower impurity concentration than the remaining portion.
According to the inventive semiconductor device fabrication method, an inventive semiconductor device in which a portion of a second doped layer adjacent to an isolation film has a lower impurity concentration than the remaining portion of the second doped layer, is reliably obtained.
The inventive semiconductor device fabrication method preferably further includes, between the steps (a) and (b), the step (d) of forming a mask pattern on the active area located in the semiconductor region and surrounded by the isolation film so that the mask pattern masks a peripheral portion of the active area. In the step (b), the first doped layer is preferably formed by implanting impurity ions with the mask pattern used as a mask.
In the inventive semiconductor device fabrication method, in the step (c), it is preferable that the second doped layer is also formed in a portion in the active area located between the first doped layer and the isolation film.
In the inventive semiconductor device fabrication method, in the step (b), the first doped layer is preferably formed in an upper portion of the active area, and in the step (c), the impurity ions are preferably implanted in such a manner that the second doped layer reaches the surface of the active area, and that in the second doped layer, a portion in the vicinity of that surface has a lower impurity concentration than the remaining portion, except the portion adjacent the isolation film.
In the inventive semiconductor device fabrication method, in the step (c), the angles with respect to the normal of the semiconductor region are preferably not less than 20 degrees.
An inventive semiconductor device includes a first doped layer and a second doped layer.
An inventive semiconductor device includes an active layer and an isolating insulator film directly connected to said active layer. Said active layer includes a high-concentration doped layer directly connected to a low-concentration doped layer having a conductivity type different than said high-concentration doped layer. A first portion of said low-concentration doped layer adjacent said isolating insulator film has an ion concentration lower than another portion of said low-concentration doped layer.
The inventive device preferably further includes an offset region located between at least a part of an outer surface of said high-concentration doped layer and said isolating insulator film.
In the inventive device, said offset region preferably includes a portion of said low-concentration doped layer.
In the inventive device, a second portion of said low-concentration doped layer adjacent a top surface of said low-concentration doped layer preferably has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive device, said low-concentration doped layer is preferably formed at least under the high-concentration doped layer.
An inventive semiconductor device includes a first doped layer and a second doped layer.
An inventive semiconductor device includes: a high-concentration doped layer, a low-concentration doped layer having a conductivity type different than said high-concentration doped layer, and an isolating insulator film. Said high-concentration doped layer is directly connected to said low-concentration doped layer and not directly connected to said isolating insulator film.
In the inventive device, a portion of said low-concentration doped layer is preferably between said isolating insulator film and said high-concentration doped layer.
In the inventive device, a portion of said low-concentration doped layer adjacent said isolating insulator film preferably has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive device, a portion of said low-concentration doped layer adjacent a top surface of said low-concentration doped layer preferably has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive device, said low-concentration doped layer is preferably formed at least under said high-concentration doped layer.
An inventive method for manufacturing a semiconductor device includes the steps of forming an isolating insulator film in a semiconductor substrate so that said isolating insulator film is connected to an active region, forming a high-concentration doped layer in the active region, and forming a low-concentration doped layer having a conductivity type different than said high-concentration doped layer so that said low-concentration doped layer is connected to said high-concentration doped layer in the active region. The step of forming a low-concentration doped layer includes forming a first portion of said low-concentration doped layer adjacent said isolating insulator film. The first portion has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer is preferably performed by rotational ion-implantation with tilt.
In the inventive method, the tilt is preferably not less than 20 degrees with respect to a line perpendicular to the surface of said semiconductor substrate.
In the inventive method, the step of forming a high-concentration doped layer preferably includes forming an offset region located between at least a part of an outer surface of said high-concentration doped layer and said isolating insulator film.
In the inventive method, said offset region preferably includes a portion of said low-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer preferably includes forming a second portion of said low-concentration doped layer adjacent a top surface of said low-concentration doped layer. The second portion has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer preferably includes forming the low-concentration doped layer at least under the high-concentration doped layer.
An inventive method for manufacturing a semiconductor device includes the steps of: forming an isolating insulator film in a semiconductor substrate, forming a high-concentration doped layer in the semiconductor substrate in such a manner that said high-concentration doped layer is not directly connected to said isolating insulator film, and forming a low-concentration doped layer having a conductivity type different than said high-concentration doped layer in the semiconductor substrate so that low-concentration doped layer is directly connected to said high-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer is preferably performed by rotational ion-implantation with tilt.
In the inventive method, the tilt is preferably not less than 20 degrees with respect to a line perpendicular to the surface of said semiconductor substrate.
In the inventive method, the step of forming a low-concentration doped layer preferably includes forming a portion of said low-concentration doped layer between said isolating insulator film and said high-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer preferably includes forming a portion of said low-concentration doped layer adjacent said isolating insulator film. The portion has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer preferably includes forming a portion of said low-concentration doped layer adjacent a top surface of said low-concentration doped layer. The portion has an ion concentration lower than another portion of said low-concentration doped layer.
In the inventive method, the step of forming a low-concentration doped layer preferably includes forming the low-concentration doped layer at least under the high-concentration doped layer.